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Integrated Circuit Systems, Inc.
ICS9159C-02
Frequency Generator and Integrated Buffer for PENTIUMTM
General Description
The ICS9159C-02 generates all clocks required for high speed RISC or CISC microprocessor systems such as 486, Pentium, PowerPC, etc. Four different reference frequency multiplying factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific applications. A test mode is provided to drive all clocks directly. High drive BCLK outputs provide typically greater than 1V/ns slew rate into 30pF loads. PCLK outputs provide typically better than 1V/ns slew rate into 20pF loads while maintaining +/-5% duty cycle.
Features
Generates up to four processor and six bus clocks, plus disk, keyboard and reference clocks Synchronous clocks skew matched to 250ps window on PCLKs and 500ps window on BCLKs Test clock mode eases system design Custom configurations available: Output frequency ranges to 100 MHz on options Selectable multiplying and processor/bus ratios Stop clock control stops clock glitch-free; available as mask option 3.0V - 5.5V supply range 28-pin SOIC package

Applications
Ideal for high-speed RISC or CISC systems such as 486, Pentium, PowerPC, etc.
Block Diagram
PLL CLOCK GEN
DISK KEYBD
X2 X1
XTAL OSC
REF(0:1) OEN
FS0 FS1
PLL CLOCK GEN
SYNC REG
PCLK(0:3) BCLK(0:5)
Pentium is a trademark of Intel Corporation PowerPC is a trademark of Motorola Corporation 9159-02 Rev D 062397
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9159C-02
Pin Configuration
Functionality
FS1 0 0 1 1 FS0 0 1 0 1 *VCO 118/17xX1 65/7xX1 92/11xX1 Test mode X1, REF (MHz) 14.318 14.318 14.318 TCLK CPU (MHz) 50(49.7) 66.6(66.5) 60(59.9) TCLK/2
*VCO range is limited from 60 - 200 MHz
28-Pin SOIC
PCLK(0,3) VCO/2 TCLK/2
BCLK(0,5) PCLK/2 TCLK/4
DISK 24 MHz TCLK/4
KEYBD 12 MHz TCLK/8
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1, 8, 14, 20, 26 2 3 4, 11, 17, 23 6, 7, 9, 10 13, 12 15, 16, 18 19, 21, 22 5 24 25 28, 27
VDD X1 X2 VSS PCLK(0:3) FS(0:1) BCLK(0:5) OEN DISK KEYBD REF(0:1)
PWR IN OUT PWR OUT IN OUT IN OUT OUT OUT
Power for logic, PCLK and fixed frequency output buffers. XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz. XTAL output which includes XTAL load capacitance. Ground for logic, PCLK and fixed frequency output buffers. Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. Bus clock outputs are fixed at one half the PCLK frequency. OEN tristates all outputs when low. This input has an internal pullup device. The DISK controller clock is fixed at 24 MHz (with 14.318 MHz input). The KEYBD clock is fixed at 12 MHz (with 14.318 MHz input). REF is a buffered copy of the crystal oscillator or reference input clock nominally 14.31818 MHz.
Note: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being supplied with 3.3 volts
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ICS9159C-02
Absolute Maximum Ratings
Supply Voltage ......................................................................................... 7.0 V Logic Inputs ..................................................... GND - 0.5 V to VDD + 0.5 V Ambient .................................................... Operating Temperature0 to +70 C Storage Temperature .................................................................. 65 to +150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stess specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current1 Output Low Current1 Output High Current1 Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage1 Supply Current
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD
TEST CONDITIONS
MIN 0.7VDD
TYP -10.5 47.0 -66.0 38.0 -47.0 0.3 2.8 0.3 2.8 55
MAX 0.2VDD 5.0 -42.0 -30.0 0.4 0.4 110
UNITS V V mA mA mA mA mA mA V V V V mA
VIN=0V VIN=VDD VOL=0.8V for PCLKS & BCLKS VOL=2.0V for PCLKS & BCLKS VOL=0.8V for fixed CLKs VOL=2.0V for fixed CLKs IOL=15mA for PCLKS & BCLKS IOH=-30mA for PCLKS & BCLKS IOL=12.5mA for fixed CLKs IOH=-20mA for fixed CLKs @66.5 MHz all outputs unloaded
-28.0 -5.0 30.0 25.0 2.4 2.4 -
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159C-02
Electrical Characteristics at 3.3 V
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
AC Characteristics
PARAMETER Rise Time1 Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute
1 1
SYMBOL Tr1 Tf1 Tr2 Tf2 Dt Tj1s1 Tjab1 Tj1s2 Tjab2 Fi CIN CINX ton ts Tsk1 Tsk2 Tsk3
TEST CONDITIONS 20pF load, 0.8 to 2.0V PCLK & BCLK 20pF load, 2.0 to 0.8V PCLK & BCLK 20pF load, 20% to 80% PCLK & BCLK 20pF load, 80% to 20% PCLK & BCLK 20pF load @ VOUT=1.4V PCLK & BCLK Clocks; Load=20pF, FOUT>25 MHz PCLK & BCLK Clocks; Load=20pF, FOUT >25 MHz Fixed CLK; Load=20pF Fixed CLK; Load=20pF
MIN 45 -250 -5 12.0
TYP 0.9 0.8 1.5 1.4 50 50 1 2 14.318 5 18 2.5 2.0 150 300 2.6
MAX 1.5 1.4 2.5 2.4 55 150 250 3 5 16.0 4.5 4.0 250 500 5
UNITS ns ns ns ns % ps ps % % MHz pF pF ms ms ps ps ns
Input Frequency Logic Input Capacitance1 Crystal Oscillator1 Capacitance1 Power-on Time1 Frequency Settling Time1 Clock Skew Window1 Clock Skew Window Clock Skew Window1
Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.5 MHz VDD supply ramp<40ms From 1st crossing of acquisition to <1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159C-02
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70oC unless otherwise stated
D C Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current 1 Output High Current1 Output Low Current 1 Output High Current1 Output Low Voltage 1 Output High Voltage 1 Output Low Voltage 1 Output High Voltage 1 Supply Current
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD VIN=0V
TEST CONDITIONS
MIN 2.4 -45 -5.0 36.0 30.0 2.4 2.4 -
TYP -15 62.0 -152 50.0 -110.0 0.25 4.0 0.2 4.7 80.0
MAX 0.8 5.0 -90.0 -65.0 0.4 0.4 160.0
UNITS V V mA mA mA mA mA mA V V V V mA
VIN=VDD VOL=0.8V; for PCLKS & BCLKS VOH=2.0V; for PCLKS & BCLKS VOL=0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL=20mA; for PCLKS & BCLKS IOH=-70mA; for PCLKS & BCLKS IOL=15mA; for fixed CLKs IOH=-50mA; for fixed CLKs @66.5 MHz; all outputs unloaded
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159C-02
Electrical Characteristics at 5.0 V
VDD = 4.5 - 5.5 V, TA = 0 - 70oC unless otherwise stated
AC Characteristics
PARAMETER Rise Time
1
SYMBOL Tr1 Tf1 Tr2 Tf2 Dt Dt2 Tj1s1 Tjab1 Tj1s2 Tjab2 Fi CIN CINX ton ts Tsk1 Tsk2 Tsk3
Fall Time1 Rise Time1 Fall Time1 Duty Cycle1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute1 Input Frequency1 Logic Input Capacitance1 Crystal Oscillator Capacitance1 Power-on Time1 Frequency Settling Time1 Clock Skew Window1 Clock Skew Window1 Clock Skew Window1
TEST CONDITIONS 20pF load, 0.8 to 2.0V PCLK & BCLK 20pF load, 2.0 to 0.8V PCLK & BCLK 20pF load, 20% to 80% PCLK & BCLK 20pF load, 80% to 20% PCLK & BCLK 20pF load @ VOUT=50% 20pF load @ VOUT=1.4V PCLK & BCLK Clocks; Load=20pF, RS=33 FOUT>25 MHz PCLK & BCLK Clocks; Load=20pF, RS=33 FOUT>25 MHz Fixed CLK; Load=20pF RS=33 Fixed CLK; Load=20pF RS=33 Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.5 MHz VDD supply ramp<40ms From 1st crossing of acquisition to <1% settling PCLK to PCLK; Load=20pF; @1.4V BCLK to BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V
MIN 45
TYP 0.55 0.52 1.2 1.1 50
MAX 0.95 0.90 2.1 2.0 55
UNITS ns ns ns ns % % ps ps % % MHz pF pF ms ms ps ps ns
-250 -5 12.0 1
50 1 2 14.318 5 18 2.5 2.0 150 300 2.6
150 250 3 5 16.0 4.5 4.0 250 500 5
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9159C-02
Ordering Information
ICS9159C-02CW28
Example:
SOIC Package
ICS XXXX - PPP XX ##
Lead Count Package Type DeviceType Prefix
Lead Count=1,2 or 3 digits CW = 0.3" Body SOIC, CS = 0.15 Body SOIC
Pattern Number(2 or 3 digit number for parts with ROM code patterns)
(consists of 3 or 4 digit numbers and one alpha code on some parts.) ICS, AV=Standard Device; GSP=Genlock device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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